BSDL Silicon Validation

Our BSDL Silicon Validation service verifies the accuracy of IEEE 1149.1/1149.6 (dot-1 / dot-6) BSDL files of a semiconductor device (large-scale ASIC and other high-density integrated circuits) both against actual silicon and syntactically and semantically, as well as eliminates a significant support issue for semiconductor suppliers.

The quality of BSDL files of your chips is essential to improving the testability of Printed Circuit Boards and systems for hardware manufacturers. When a BSDL file is inaccurate or the implementation of Boundary-Scan (JTAG) in a device is poorly executed, testing or programming the device will require additional time and effort to troubleshoot. Moreover, in the worst case, an inaccurate BSDL file will reduce Boundary-Scan (JTAG) test coverage in every product where the device is designed-in. Once a BSDL file has been syntactically and semantically validated and first samples of the semiconductor device have been produced, the accuracy of the BSDL file can be verified against actual silicon with StarTest™'s BSDL Silicon Validation Service.

The device-under-test (DUT) is placed in a fixture or assembled on an intended BSDL Validation Board (BVB) that provides proper Power and Ground, Boundary-Scan (JTAG) access to each I/O, access to the TAP pins (/TRST, TMS, TCK, TDI, and TDO) and static control of compliance enable pins (if applicable). The BVB provides abundant JTAG test coverage for even the highest density BGA packages, as well as Multi-Chip-Modules (MCM) and System-on-Chip (SOC) designs. Utilizing the high-speed JTAG controller, the BVB achieves TCK speeds up to 70 MHz and runs against the silicon both gated TCK and free-running TCK. The BVB also offers excellent flexibility due to its four banks of adjustable voltage levels.

The BSDL Silicon Validation is performed for the five worldwide most usable JTAG vendor platforms:

ScanExpress TPG and Runner (Corelis); ScanWorks TPG and Runner (Asset Intertech); ProVision TPG and Runner (JTAG Technologies); Cascon Galaxy TPG and Runner (Goepel Electronic); onTAP TPG and Runner (Flynn Systems); XJDeveloper and XJRunner (XJTAG).

The maximum stable TCK frequency for each JTAG platform hardware will be validated. You can supply your customer the BSDL file with the following heading as the result of the validation:

This BSDL has been successfully validated by StarTest™ validation process;for the IEEE 1149.1 / IEEE 1149.6 compliance with the following; JTAG vendor platforms:

A test sequence is generated for the BVB to empirically validate that its embedded JTAG/Boundary-Scan capabilities are described accurately in its BSDL file. The test consisting of:

TAP Reset (both hard with /TRST and soft); Instruction Register (IR) Capture Test; Bypass Register Test; IDCODE Register Verification; Boundary-Scan Register (BSR) Length Check; USERCODE (if applicable); Interconnect/Pin Test (EXTEST Instruction Test per I/O pin).

The StarTest™ personnel will perform PRELOAD/EXTEST instructions for each I/O of your semiconductor device to verify the accuracy of the contents of the BSDL file and to validate  a l l  Boundary-Scan cells are working properly. Each Input, Output and Bi-directional pin is fully tested for shorts and stuck-at-1 and stuck-at-0 faults. All applicable drivers are tested, and all applicable receivers are tested. Bi-directional pins are tested in both directions for all faults (shorts & stuck-ats). Directional control cells are tested against their enable and disable state of the BSDL. If any anomalies are found, the BSDL file is corrected and the device is re-tested.

The pin-specific tests are the following:

The in-device ball pull-up/pull-down resistors testing The pin voltage tolerance testing, i.e. the dependence between vendor-declared IC voltage tolerance range and the correct JTAG functioning of each IC pin.

The BVB is also intended for the IEEE 1149.6 (dot-6, Advanced EXTEST) Standard BSDL Silicon Validation. The 1149.6 BSDL Validation process consisting of:

Syntax Checking for 1149.6 Expanded 1149.6 Opcode Instructions Expanded 1149.6 Cell Types Advanced I/O Attributes 1149.6 Output Cells Verify that DUT can properly execute 1149.6 related instructions EXTEST_PULSE Instruction: DUT produces correct waveform of single pulse EXTEST_TRAIN Instruction: DUT produces correct waveform of multiple pulses Verify 1149.6 output signals from DUT can be properly detected on BVB 1149.6 receiver cells Validate both dot-1 and dot-6 cell types are mapped to the correct package pins on DUT 1149.6 Input Cells Verify that DUT can properly detect 1149.6 signal modes EXTEST_PULSE Instruction: DUT properly detects single pulse EXTEST_TRAIN Instruction: DUT properly detects multiple pulses Verify that DUT can properly detect 1149.1 DC signal if configured with AC selection mode 1149.6 Special Control Cells Verify that DUT dot-6 Output Cells can be controlled by AC Selection Cells Verify dot-6 Input/Output Cells Support dot-1 when respective control cell is in deselected mode

We trust you will find it helpful in improving the quality of your BSDL files and silicon. Our service can quickly spot JTAG insertion and BSDL errors and is an excellent way to prevent Boundary-Scan (JTAG) testability problems in the field.

Until now, very expensive semiconductor testers and test fixtures were used to perform a semiconduc-tor device BSDL verification functions. Our service performs most of these functions at a fraction of the cost.

We would be pleased to discuss any of your evaluation or reference
board design and test challenges to see if these would be a fit.